Comments on: Apply the Scientific Method to IC Design Flow

By: Giovanni de Micheli

Giovanni de Micheli — Tue, 04 May 2010 18:46:16 +0000

Dear John,
I would like to ask your permission to use the picture of the Calma Layout system and operator in a short paper for the IEEE SSCS magazine. I can give
you full credit. Please let me know if this is fine for you.

Best regards
Giovanni De Micheli

By: Control Your IC Design Flow — Voom, Inc.

Control Your IC Design Flow — Voom, Inc. — Fri, 07 Aug 2009 05:44:47 +0000

[...] Apply the Scientific Method to IC Design Flow [...]

By: Creating a Self-Documenting File Hierarchy — Voom, Inc.

Creating a Self-Documenting File Hierarchy — Voom, Inc. — Tue, 26 May 2009 04:30:51 +0000

[...] is one of a series of articles on scientific IC design flow–simple, specific techniques that make your flow easy to [...]

By: Log File Naming for EDA Tools — Voom, Inc.

Log File Naming for EDA Tools — Voom, Inc. — Sun, 22 Mar 2009 06:01:19 +0000

[...] This is one of a series of articles on IC design flow construction rules. [...]

By: Writing Effective Error Messages — Voom, Inc.

Writing Effective Error Messages — Voom, Inc. — Sun, 22 Mar 2009 06:00:00 +0000

[...] This is one of a series of articles on IC design flow construction rules. [...]